1. Technical Field of The Invention
This disclosure relates to semiconductor memory devices and more particularly, to non-volatile semiconductor memory devices with flexible redundancy schemes.
2. Description of the Related Art
As semiconductor memory devices follow the trend of increased integration density, chip sizes continue to shrink. Reduced product yields arise because of the increasing complexity of manufacturing processes. The reduced product yield of semiconductor devices is mostly responsible for defects of memory cells.
The redundancy technique, where defective cells are substituted with redundant cells virtually in situ, is a widely adopted way to enhance the product yield despite memory cell defects. Some kinds of memory cells are normally usable even with several defects in their cell arrays, referring to their specifications (i.e., data books) defining the permissible number of defective memory cells therein. For example, NAND flash memory devices, unlike DRAMs or SRAMs, are still capable of functioning even though there are defective memory cells in part of the array.
FIG. 1 shows a structure of a typical semiconductor memory cell array having redundant cell blocks. Referring to FIG. 1, a memory cell array is divided into a main cell area 10 and a redundant cell area 20. The main cell area 10 is composed of 1,024 main memory cell blocks and the redundant cell area 20 is composed of 16 redundant memory cell blocks. The main and redundant memory cell blocks both have the same structure.
The main cell blocks of the main cell area 10 correspond to adjacent row decoders while the redundant cell blocks of the redundant cell area 20 correspond to adjacent redundant decoders, where the decoders control rows of their corresponding cell blocks.
Even in a NAND flash memory device that is operable in a condition with defective cell blocks or bad blocks within a specified number, it may occur that the number of bad blocks is greater than the number of redundant cell blocks embedded therein. If a K'th main cell block is detected as a new bad block after all redundant cell blocks have already been exhausted by substitution for other bad blocks, the position of the new bad block must be designated in order to operate the over-failed NAND flash memory device in a normal manner, without disturbance while addressing the cell blocks.